Previously, a metallic oxide dielectric has been used as a capacitor insulating film of a semiconductor memory device because it has high dielectric properties and/or high ferroelectric properties. For example, the metallic oxide dielectric may contain a layer of bismuth oxide SrBi.sub.2 Ta.sub.2 O.sub.9 or titanium zirconate (Pb(Ti, Zr)O.sub.3) to exhibit the ferroelectric properties. If the metallic oxide dielectric is exposed to a reducing atmosphere, crystallized metal ions are reduced while oxide ions are released, and thus, oxide defects are formed in the dielectric. As a result, various characteristics of the metal oxide dielectric deteriorate (e.g. an increase in leak current, a degradation of remanence characteristics, etc.). Accordingly, when a capacitor having a metallic oxide dielectric is mounted on a silicon integrated circuit, the capacitor should be prevented from being exposed to a reducing atmosphere as much as possible during the manufacturing process of the integrated circuit.
Also, a noble or inert metal such as platinum ("Pt") which resists oxidation should be used as an electrode of the capacitor having the metal oxide dielectric. Therefore, one must be careful to prevent a reaction between such metal forming the capacitor electrode and the metal wiring which is electrically connected to the capacitor electrode. If the two metals react, the properties of the capacitor deteriorate.
In order to better understand the concepts described above and to even further appreciate the achievements of the present invention, three conventional examples will be described below.
The first conventional example is disclosed in H. Kokie, et al., "A 60-ns 1-Mb Nonvolatile Ferroelectric Memory with a Nondriven Cell Plate Line Write/Read Scheme", IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, (Nov. 1996). The first conventional example is illustrated in FIGS. 19 to 26 and shows a method of manufacturing a ferroelectric memory device using titanium zirconate ("PZT") as a metal oxide dielectric. As described above, PZT has high ferroelectric properties.
As shown in FIG. 19, the ferroelectric memory device is roughly partitioned into a memory cell array section 34 and a peripheral CMOS circuit section 33. In the memory cell array section 34, ferroelectric capacitors are regularly disposed. Also, the peripheral CMOS circuit section 33 includes CMOS transistor units that each contain a p-type MOS ("PMOS") transistor 8 and an n-type MOS ("NMOS") transistor 7 as a unit.
As shown in FIG. 20, the device is manufactured by providing a silicon substrate 1 having a memory cell array section 34 and a peripheral CMOS circuit section 33. Then, a memory cell array containing n-type MOSFETs is formed in the memory cell array section 33, and PMOS transistors 7 and NMOS transistors 8 are formed in the peripheral CMOS circuit section 33. Each of the MOS transistors in the device comprises a silicon doping layer or a source/drain region formed in silicide and comprises a gate electrode 5.
After the MOS transistors are formed, a silicon oxide film (i.e. an NSG film) 9 is grown over the transistors via a chemical vapor deposition ("CVD") process, and a boron phosphorus added silicon oxide ("BPSG") film 10 is grown on the NSG film 9 via a CVD process. After the BPSG film 10 is grown, it is reflowed and flattened.
Then, as shown in FIG. 21, a Ti electrode adhesive film 11 and a Pt lower capacitor electrode film 12 are sequentially formed on the BPSG film 10 via a sputtering process, and a PZT precursor is formed on the Pt lower capacitor electrode 12 via a spin coating method. Then, the PZT precursor is crystallized into a PZT film 13 by subjecting the precursor to an annealing process at about 600.degree. C. A photoresist 15 having a pattern corresponding to the shape of the Pt lower capacitor electrode 12 of the capacitor is then formed on the PZT film 13.
Then, as shown in FIG. 22, portions of the PZT film 13, the Pt lower capacitor electrode film 12, and the Ti electrode adhesive film 11 are removed via an ion milling process, and the photoresist 15 is peeled off of the remaining portions of the PZT film 13. Afterwards, a first recovery annealing process is conducted in an oxygen atmosphere for eliminating the etching damage caused by the ion milling process and the removal of the photoresist 15.
As shown in FIG. 23, a Pt upper capacitor electrode film 14 is formed via a sputtering process, and a photoresist 15 that is patterned according to the shape of the upper electrode of the capacitor is formed on the film 14. Then, portions of the film 14 are removed by conducting an ion milling process while using the photoresist 15 as a mask to form the upper electrode 14 of the capacitor. As a result, a ferroelectric capacitor 16 is formed via the Ti electrode adhesive film 11, the Pt lower capacitor electrode 12, the PZT film 13 (i.e. the metal oxide dielectric), and the Pt upper capacitor electrode 14. Afterwards, a second recovery annealing process is conducted in an oxide atmosphere to remove the etching damage formed by the ion milling process and the removal of the photoresist 15. As shown in FIG. 24, a capacitor cover insulating film (i.e. a silicon oxide film) 19 is formed on the ferroelectric capacitor 16 via a plasma CVD method using silane gas (SiH.sub.4) and oxygen gas as a raw material.
As shown in FIG. 25, transistor contact holes (i.e. first contact holes) 20 and capacitor contact holes (i.e. second contact holes) are formed in the semiconductor device. The first contact holes 20 extend to the gate electrodes and the source/drain regions of the MOS transistors, and the second contact holes 22 extend to the upper capacitor electrode 14 and the lower capacitor electrode 12 of the capacitors 16. Such holes 20 and 22 are created via a patterning process while using a photoresist (not shown) as a mask. After the holes 20 are created, a laminating film 21 consisting of a Ti adhesive film and a first barrier film of TiN is formed over the entire surface via a sputtering method.
In FIG. 26, an Al wiring metal film 26 and a TiN reflection preventing film 25 are sequentially formed on the entire surface. Then, the first layer Al wiring 26, the TiN reflection preventing film 25, and the laminate film 21 are patterned via a known process using a mixed gas consisting of Cl.sub.2 and BCl.sub.3.
As shown in FIG. 19, an interlayer insulating film 27 is formed on the patterned first layer Al wiring 26, and through-holes 28 are formed in the film 27 that extend to the first layer Al wiring 26. Then, tungsten 32 is embedded in the through-holes 28 by growing tungsten 32 via a CVD method and etching back the tungsten 32. Then, a second layer Al wiring 30 is formed over the interlayer insulating layer 27 and the tungsten 32.
The second conventional example is disclosed in FIG. 13 of Japanese Patent Unexamined Publication No. Hei 6-275792. The second conventional example is illustrated in FIGS. 27 to 31 and shows a method of manufacturing a ferroelectric memory device having a metal oxide dielectric.
As shown in FIG. 27, a BPSG film 10 is formed over MOS transistors and is flattened. Then, a Ti electrode adhesive film 11 is formed on the BPSG film 10, and a Pt lower capacitor electrode film 12 is formed on the adhesive film 11. Then, the portions of the adhesive film 11 and electrode film 12 are removed to form the lower capacitor electrode 12 of the capacitor.
As shown in FIG. 28, a PZT film 13 is grown over the surface of the semiconductor device, and a Pt upper capacitor electrode film 14 is grown over the PZT film 13. Then, a photoresist 15 having a pattern corresponding to the upper capacitor electrode of the capacitor is formed over the Pt upper capacitor electrode film 14, and portions of the PZT film 13 and the electrode film 14 are removed using the photoresist 15. As shown in FIG. 29, the photoresist 15 is removed, and a ferroelectric capacitor 16 is formed by the Pt lower capacitor electrode film 12, the PZT film 13, and the Pt upper capacitor electrode film 14. Subsequently, as shown in FIG. 30, a Ti film is formed on the entire surface of the semiconductor device, and the film is patterned by a dry etching process to form a Ti barrier metal pattern 35 on the Pt lower capacitor electrode film 12 and the Pt upper capacitor electrode film 14.
As shown in FIG. 31, a capacitor cover insulating film 19 is formed over the ferroelectric capacitor 16 via a CVD method, and transistor contact holes (i.e. first contact holes) 21 and capacitor contact holes (i.e. second contact holes) 22 are formed through the insulating film 19. Furthermore, an Al--Si layer is grown on the entire surface of the semiconductor device via a sputtering process, and a first-layer Al wiring 26 is formed by performing a dry etching process on the Al--Si layer.
As shown in the second conventional example, by forming the Ti barrier metal pattern 35 on the Pt lower capacitor electrode film 12 and the Pt upper capacitor electrode film 14 (FIGS. 30 and 31), the first-layer Al wiring 26 is prevented from directly contacting the Pt lower capacitor electrode film 12 and the Pt upper capacitor electrode film 14.
The third conventional example is disclosed in FIG. 1 of Japanese Patent Unexamined Publication No. Hei 5-90606. The third conventional example is illustrated in FIGS. 32 to 34 and shows a method of manufacturing a ferroelectric memory device.
As shown in FIG. 32, an interlayer insulating film 36 is formed over MOS transistors, and a Ti electrode adhesive film 11 and a Pt lower capacitor electrode film 12 are sequentially formed over the interlayer insulating film 36. Then, portions of the adhesive film 11 and electrode film 12 are removed via a patterning process, and a PZT film 13 is grown on the entire surface. Afterwards, the PZT film 13 is etched so that it is slightly larger than the Pt lower capacity electrode film 12.
As shown in FIG. 33, a Pt upper capacitor electrode film 14 and a TiN upper electrode barrier film 37 are sequentially grown on the entire surface of the semiconductor device. Then, the is films 14 and 37 are dry-etched to form an upper capacitor electrode having a laminated structure. Afterwards, as shown in FIG. 34, a capacitor cover insulating film 19 is grown over the entire surface, and transistor contact holes (i.e. first contact holes) 20 and capacitor contact holes (i.e. second contact holes) 22 are formed in the insulating film 19. Also, the first contact holes 20 extend to the MOS transistors, and the second contact holes 22 extend to the TiN upper electrode barrier film 37 of the upper capacitor electrode 14. Then, an Al layer is sputtered on the entire surface of the semiconductor device, and a first-layer Al wiring 26 is formed by dry etching the Al layer.
As shown above in the third conventional example, the upper capacitor electrode is formed from a laminate film comprising a Pt upper capacitor electrode film 14 and a TiN upper electrode barrier film 37 formed on the electrode film 14. Therefore, when the, Al wiring 26 is formed, the wiring 26 does not directly contact the Pt upper capacitor electrode 14.
The devices described in the conventional examples above have several disadvantages. For example, in the first conventional example, after the capacitor cover insulating film 19 is formed over the entire surface (FIG. 24), the first contact holes (i.e. transistor contact holes) 20 and the second contact holes (i.e. capacitor contact holes) 22 are simultaneously formed through the insulating film (FIG. 25). When the contact holes are initially being formed, a gas (i.e. a CF.sub.4 plasma gas) having a high etching speed and a small selectivity between the insulating film and the silicon doping layer below the insulating film is used to reduce the time required to etch the insulating film. However, in order to ensure that the etching process does not actually etch the silicon doping layer below the insulating film, a gas (i.e. a CHF.sub.3 plasma gas) having a low etching rate and a high selectivity between the insulating film and the silicon doping layer is used to finish the etching process. Since a CHF.sub.3 plasma gas is used, hydrogen radicals and hydrogen ions in the gas contact the ferroelectric capacitor 16 via the capacitor contact holes 22 and reduce the size of the PZT film 13. As a result, the characteristics of the capacitor 16 are deteriorated.
Also, in a typical LSI manufacturing process, after a photoresist is peeled off of the semiconductor device, an SPM cleaning process and an APM cleaning process are performed to eliminate etching damage. The SPM cleaning process is performed by using a liquid mixture consisting of sulfuric acid and hydrogen peroxide water, and the APM cleaning process is performed by using a liquid mixture consisting of ammonium water and hydrogen peroxide water.
However, in the first conventional example, after the photoresist used to form the contact holes 20 and 22 is peeled off (FIGS. 24 to 25), the Pt lower capacitor electrode film 12 and the Pt upper capacitor electrode film 14 are located at the bottom of the second contact holes (capacitor contact holes) 22. As a result, the SPM cleaning process or the APM cleaning process cannot be performed. Specifically, the SPM and APM cleaning processes use solutions which dissolve small amounts of platinum Pt that diffuse into the doped region and degrade the performance of the transistor. As a result, an organic cleaning process using an organic solvent such as methyl ethyl ketone is used. However, the organic cleaning process is not as effective as the SPM and APM cleaning processes, and thus, an organic fluoride (not shown) deposited in the bottom of the first contact hole (i.e. the transistor contact hole) 20 when the holes 20 were previously etched with CHF.sub.3 plasma cannot be sufficiently removed. Therefore, the electrical current flowing from the first layer Al winding 26 to a MOS transistor via the contact holes 20 may be blocked.
Also, in the first conventional example, after the first and second contact holes 20 and 22 are formed, a laminate film 21 containing a Ti adhesive film and a first barrier film (TiN) is grown on the entire surface of the device (FIG. 25). In such case, the Pt upper capacitor electrode film 14 directly contacts the Ti adhesive film at the bottom of the second contact hole (capacitor contact hole) 22. Therefore, Ti is diffused into the Pt upper capacitor electrode film 14 and reaches the surface of the PZT film 13. As a result, the Ti reacts with oxygen in the PZT crystals in the film 13 to form TiO.sub.x, and thus, oxygen defects are generated in crystals of the PZT film 13 and deteriorate the characteristics of the transistor 16.
Also, in the first conventional example, the photoresist 15 which is used as a mask to form the first and second contact holes 20 and 22 is removed by directly exposing the photoresist 15 to oxygen plasma using microwaves. In such case, hydrogen contained in an organic compound forming the photoresist 15 is converted into hydrogen radicals and/or hydrogen ions by the microwaves. Thus, the hydrogen radicals and/or ions contact the ferroelectric capacitor 16 via the contact holes 22 and reduce the PZT film 13, and thus, the characteristics of the capacitor 16 are deteriorated.
Also, in the first conventional example, a tungsten plug 32 is formed by embedding tungsten into the through-hole 28 that connects the first Al wiring 26 and second Al wiring 30 via a metal CVD process (FIG. 19). In order to form the tungsten, a WF.sub.6 gas is mixed with a silane gas (i.e. SiH.sub.4) or a hydrogen gas (i.e. H.sub.2) to form the tungsten W. However, during such process, a HF gas or SiF.sub.x H.sub.y gas is created as a byproduct gas which is easily diffused into the PZT film 13 of the capacitor 16. The byproduct gas reacts with the PZT film 13 to create oxygen defects in the film 13, and thus, the characteristics of the capacitor 16 are deteriorated.
With respect to the second conventional example, a capacitor 16 having a Pt upper capacitor electrode film 14 and a lower capacitor electrode film 12 is formed (FIG. 29). Then, a Ti barrier metal pattern 35 is formed on the Pt lower and upper capacitor electrode films 12 and 14 (FIGS. 30). The Ti barrier metal pattern 35 prevents the first Al wiring 26 from directly contacting the electrode films 12 and 14. However, since the Ti barrier metal pattern contains Ti, Ti diffuses into the PZT film 13 and causes oxygen defects to occur in the crystal of the PZT film 13. Also, the PZT crystal is deteriorated when the Ti barrier metal pattern 35 is grown on the ferroelectric capacitor 16 via the sputtering process. As a result, the characteristics of the capacitor 16 are deteriorated.
With respect to the third conventional example 3, the laminate electrode film consisting of the Pt upper capacitor electrode film 14 and the upper electrode barrier film 37 is grown on the PZT film 13, and then, then the electrode film 14 and the barrier film 37 are patterned together to obtain a structure in which the upper electrode barrier film 37 is aligned with the Pt upper capacitor electrode film 14 (FIG. 33). However, in general, after a PZT capacitor 16 is patterned, oxygen atmospheric annealing is conducted to eliminate etching damage. However, in the situation of the third conventional example, since the TiN upper electrode barrier film 37 will oxidize if it is subjected to oxygen, the oxygen annealing process can not be performed after the ferroelectric capacitor 16 is created.